The present invention relates to a process of fabricating a semiconductor device including a step of forming a silicide layer.
In the transistor field, it has been increasingly required to make shallower diffusion layers with a thrust toward finer-line geometries of devices. More specifically, because of a tendency to reduce gate line widths, a short-channel effect increases unless a diffusion layer is made considerably shallow in depth. For example, in the case of a transistor having a gate line width of 0.25 .mu.m, the depth of a diffusion layer is required to be as shallow as about 0.08 .mu.m.
With such a tendency to make shallower a diffusion layer, a sheet resistance in a source/drain region of a transistor is increased, with a problem that a response speed of the device is degraded. Now, letting .pi.pd be a gate delay time, an operational frequency "f" is related to 1/.pi.pd, and accordingly, if the response speed is degraded, the operational frequency cannot be expected to be improved. This situation is particularly inconvenient for a microprocessor unit (MPU) requiring a high speed operation. To cope with such an inconvenience, there has been proposed a process for selectively forming a titanium silicide (TiSi.sub.2) having a low resistance only on a source/drain region.
Here, one example of a related art MOS (Metal-Oxide-Semiconductor) LSI fabrication process will be described with reference to a sequence of fabrication steps shown in FIGS. 10A to 10C.
A MOS transistor is formed by a known process shown in FIG. 10A. Element isolation regions 112 are formed in a semiconducting substrate 111, followed by formation of a gate insulating film 113 on the semiconducting substrate 111, and a gate interconnection 114 is formed on the gate insulating film 113. LDD (Lightly doped Drain) regions 115, 116 are formed in the semiconducting substrate 111 on both sides of the gate interconnection 114, and side wall insulating films 117, 118 are formed on side walls of the gate interconnection 114. Subsequently, ions of a conducting type impurity are doped in the semiconducting substrate 111 by ion implantation, followed by RTA (Rapid Thermal Annealing) as activating heat treatment, to form source/drain regions 119, 120 in the semiconducting substrate 111 on both the sides of the gate interconnection 114. In this activating heat treatment, heating is performed at a temperature rising rate of about 100.degree. C./sec and cooling is performed at a temperature dropping rate of about 100.degree. C./sec. A MOS transistor 101 is thus formed.
As shown in FIG. 10B, a natural oxide film (not shown) on the source/drain regions 119, 120 are perfectly removed by subjecting the semiconducting substrate 111 to hydrofluoric acid (HF) treatment, and a titanium (Ti) film is formed over the entire surface to a thickness of 50 nm by, for example, sputtering. After that, the semiconducting substrate 111 in such a state is subjected to heat treatment in two stages (first heat treatment: 500.degree. C. in a nitrogen atmosphere, second heat treatment: 800.degree. C. in a nitrogen atmosphere), to selectively form low resistance titanium silicide (TiSi.sub.2) layers 121, 122, 123 by reaction of silicon contained in the source/drain regions 119, 120 and the gate interconnection 114 with titanium (Ti) contained in the titanium film.
The semiconducting substrate 111 is immersed, for example, in a solution of ammonia and hydrogen peroxide to selectively etch a non-reactant portion (not shown) of the titanium film.
As shown in FIG. 10C, an interlayer insulating film 131 made of silicon oxide is formed on the semiconducting substrate 111 so as to cover the MOS transistor 101 by, for example, CVD (Chemical vapor Deposition). A contact hole 132 is formed in the interlayer insulating film 131 on, for example, the source/drain region 120 by lithography and etching, and a tungsten plug 134 is formed in the contact hole 132 via an adhesive layer 133 by a known blanket tungsten plug process. Then, an adhesive layer 141 and an interconnection layer 142 formed of an aluminum alloy (for example, aluminum-silicon) film are formed on the interlayer insulating film 131 in a state being connected to the tungsten plug 134. Finally, the adhesive layer 141 and the interconnection layer 142 are patterned by lithography and etching, to form an interconnection 143.
The device formed in accordance with the above-described process has an advantage that a resistance of each of the source/drain regions 119, 120 can be reduced by about one digit as compared with a conventional structure having no titanium silicide.
The above-described process, however, has a problem. Namely, in recent years, it is increasingly required to make diffusion layers finer with the thrust toward finer-line geometries of devices, as a result of which a titanium silicide must be formed in a narrow source/drain region, tending to be aggregated, thus making it impossible to reduce the sheet resistance. In particular, it becomes difficult to reduce the sheet resistance for a diffusion region having a width of 0.5 .mu.m or less.
Hereinafter, the mechanism in which titanium silicide is aggregated will be described.
Titanium silicide has two crystal phases: one containing high resistance C49 type crystals, and the other containing low resistance C54 type crystals. In general, titanium silicide having the above two crystal phases is formed by heat treatment in two stages.
A first stage heat treatment is performed at a relatively low temperature at which titanium (Ti) does not react with an insulating film but reacts with silicon (Si), to form titanium silicide having the C49 type crystal phase.
The non-reactant titanium is removed.
Then, a second stage heat treatment is performed at a relatively high temperature, to convert the titanium silicide from the C49 type crystal phase to the C54 type crystal phase having a low resistance.
In a fine width region (for example, a region having a width less than 0.5 .mu.m), however, the C49 type crystal phase is not converted into the C54 type crystal phase, and consequently, in the second stage heat treatment, the C49 type crystals having a high resistance are aggregated.
Additionally, with a tendency to make shallower a diffusion layer, it is necessary to make thin a titanium silicide film formed on the diffusion layer. However, the thinning of a titanium silicide film causes aggregation of titanium silicide formed on the diffusion layer, thereby making it more difficult to reduce the sheet resistance of the diffusion layer at a narrow portion.
To prevent the aggregation of titanium silicide, there may be considered a process of implanting ions of arsenic in a region of a semiconducting substrate on which silicide is to be formed, thereby making the region amorphous.
In this process, however, since the radius of an arsenic ion is large, oxygen in a natural oxide film formed on the surface of the silicon substrate is knocked-on into the silicon substrate by ions of arsenic, to thereby cause aggregation of silicide upon silicide formation.
The related art process including the step of forming a silicide layer also has the following important problem. Namely, as shown in FIG. 11, stress concentration regions S are produced in the silicon substrate 111 at the ends of the side wall insulating film 117 (118) and the ends of the element isolation region 112 after formation of the titanium silicide layer 121 (122). In this region S, crystal dislocations or the like are generated. Moreover, crystal defects F are produced by ion implantation, and they cannot be sufficiently recovered only by RTA as the activating heat treatment, leading to generation of leak current.
More specifically, in the activating heat treatment for the source/drain region 119 (120), the temperature rising rate is as high as 100.degree. C./sec and the temperature dropping rate is as high as 100.degree. C./sec, so that the crystal defects F produced by ion implantation cannot be sufficiently recovered by the activating heat treatment.